1. Field of the Invention
This invention is related to the field of integrated circuits and, more particularly, to memories in integrated circuits.
2. Description of the Related Art
As the number of transistors included on a single integrated circuit “chip” has increased and as the operating frequency of the integrated circuits has increased, the management of power consumed by an integrated circuit has continued to increase in importance. If power consumption is not managed, meeting the thermal requirements of the integrated circuit (e.g. providing components required to adequately cool the integrated circuit during operation to remain within thermal limits of the integrated circuit) may be overly costly or even infeasible. Additionally, in some applications such as battery powered devices, managing power consumption in an integrated circuit may be key to providing acceptable battery life.
One mechanism for managing power may including idling portions of the integrated circuit that are not in use. In the case of an on-chip memory such as a cache or embedded memory, idling the memory typically includes holding the bit lines in the memory in a precharge state by keeping the bit line precharge circuits active. However, there may be a significant amount of leakage current in the inactive transistors within the memory, and the active precharge circuits supply charge that can be further leaked, consuming power. Additionally, transistors are subject to aging effects such as negative bias temperature instability (NBTI). Keeping the precharge circuit transistors active during long idle periods can lead to significant NBTI. Accordingly, the precharge circuit transistors are typically designed to be larger than they would otherwise need to be, so that they can precharge the bit lines effectively even after NBTI effects have started to accumulate.